Difference between revisions of "Kaustubh Shivdikar"
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+ | ======[[https://wiki.kaustubh.us/w/img_auth.php/resume.pdf Resume]]====== | ||
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====Education==== | ====Education==== | ||
− | *PhD - Computer Engineering, Northeastern University [ | + | *PhD - Computer Engineering, Northeastern University [May 2024] |
*MS - Electrical and Computer Engineering, Northeastern University [May 2021] | *MS - Electrical and Computer Engineering, Northeastern University [May 2021] | ||
*BS - Electrical Engineering, Veermata Jijabai Technological Institute [May 2016] | *BS - Electrical Engineering, Veermata Jijabai Technological Institute [May 2016] | ||
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*''Summer-Fall 2018 Coop:'' Mobile Robotics @ [https://www.adept.com/home/?region=us Omron Adept] with [https://www.linkedin.com/in/georgevpaul/ George Paul]. | *''Summer-Fall 2018 Coop:'' Mobile Robotics @ [https://www.adept.com/home/?region=us Omron Adept] with [https://www.linkedin.com/in/georgevpaul/ George Paul]. | ||
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==Recent News== | ==Recent News== | ||
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*June 2022: Mentored Lina Adkins for the GNN Acceleration project at [https://stem.northeastern.edu/summer/reu/pathways/students/ REU-Pathways] program | *June 2022: Mentored Lina Adkins for the GNN Acceleration project at [https://stem.northeastern.edu/summer/reu/pathways/students/ REU-Pathways] program | ||
− | *May 2022: Served as '''Submission chair''' for [https://hpca-conf.org/2023/ HPCA 2023] conference. | + | *May 2022: Served as '''Submission co-chair''' for [https://hpca-conf.org/2023/ HPCA 2023] conference. |
*Jan 2020: '''Taught''' the GPU Programming Course at NEU | *Jan 2020: '''Taught''' the GPU Programming Course at NEU | ||
*April 2019: '''[https://coe.northeastern.edu/news/congratulations-rise2019-winners/ Graduate Innovator Award]''' at the RISE 2019 Research Expo for our poster Pi-Tiles | *April 2019: '''[https://coe.northeastern.edu/news/congratulations-rise2019-winners/ Graduate Innovator Award]''' at the RISE 2019 Research Expo for our poster Pi-Tiles | ||
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+ | ==Publications== | ||
+ | [[File:neuracore.png|right|frameless|76x76px|NeuraCore Image]] | ||
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+ | ======[https://wiki.kaustubh.us/w/img_auth.php/NeuraChip_GNN_Accelerator.pdf NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator]====== | ||
+ | {{Nutshell|Decoupled multiplication and addition operations to speedup GNNs.|title=NeuraChip}} | ||
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+ | (ISCA 2024) [[https://wiki.kaustubh.us/w/img_auth.php/NeuraChip_GNN_Accelerator.pdf PDF]] [[https://www.researchgate.net/publication/380127919_NeuraChip_Accelerating_GNN_Computations_with_a_Hash-based_Decoupled_Spatial_Accelerator RG]] [Slides] [[https://github.com/NeuraChip/neurachip GitHub]] [[https://neurachip.us/ Website]] | ||
+ | |||
+ | ==.== | ||
+ | [[File:gpu icon.png|right|frameless|93x93px]] | ||
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+ | ======[https://wiki.kaustubh.us/w/img_auth.php/Graph_Accelerator_Thesis.pdf Enabling Accelerators for Graph Computing]====== | ||
+ | {{Nutshell|Software and Hardware enhancements for GNNs|title=Thesis}} | ||
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+ | (Ph.D. Thesis) [[https://wiki.kaustubh.us/w/img_auth.php/scalability_limitations.pdf PDF]] | ||
+ | ==.== | ||
+ | [[File:PIM Logo.png|alt=Scalability Limitations of Processing-in-Memory using Real System Evaluations|right|frameless|83x83px]] | ||
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+ | ======[https://wiki.kaustubh.us/w/img_auth.php/scalability_limitations.pdf Scalability Limitations of Processing-in-Memory using Real System Evaluations]====== | ||
+ | {{Nutshell|Suggest interconnects for PIM nodes to enable efficient all-to-all communication.|title=Paper}} | ||
− | == | + | ([https://dl.acm.org/doi/abs/10.1145/3639046 ACM SIGMETRICS 2024]) [[https://wiki.kaustubh.us/w/img_auth.php/scalability_limitations.pdf PDF]] [[https://www.researchgate.net/publication/378386110_Scalability_Limitations_of_Processing-in-Memory_using_Real_System_Evaluations RG]] |
− | [[File: | + | {| class="wikitable mw-collapsible mw-collapsed" |
+ | |+Abstract | ||
+ | !Abstract | ||
+ | |- | ||
+ | |Processing-in-memory (PIM), where the compute is moved closer to the memory or the data, has been widely explored to accelerate emerging workloads. Recently, different PIM-based systems have been announced by memory vendors to minimize data movement and improve performance as well as energy efficiency. One critical component of PIM is the large amount of compute parallelism provided across many PIM “nodes” or the compute units near the memory. In this work, we provide an extensive evaluation and analysis of real PIM systems based on UPMEM PIM. We show that while there are benefits of PIM, there are also scalability challenges and limitations as the number of PIM nodes increases. In particular, we show how collective communications that are commonly found in many kernels/workloads can be problematic for PIM systems. To evaluate the impact of collective communication in PIM architectures, we provide an in-depth analysis of two workloads on the UPMEM PIM system that utilize representative common collective communication patterns – AllReduce and All-to-All communication. Specifically, we evaluate 1) embedding tables that are commonly used in recommendation systems that require AllReduce and 2) the Number Theoretic Transform (NTT) kernel which is a critical component of Fully Homomorphic Encryption (FHE) that requires All-to-All communication. We analyze the performance benefits of these workloads and show how they can be efficiently mapped to the PIM architecture through alternative data partitioning. However, since each PIM compute unit can only access its local memory, when communication is necessary between PIM nodes (or remote data is needed), communication between the compute units must be done through the host CPU, thereby severely hampering application performance. To increase the scalability (or applicability) of PIM to future workloads, we make the case for how future PIM architectures need efficient communication or interconnection networks between the PIM nodes that require both hardware and software support. | ||
+ | |- | ||
+ | |[[File:Scaling PIM.png|frameless|748x748px]] | ||
+ | |- | ||
+ | |'''Authors''': Gilbert Jonatan, Haeyoon Cho, Hyojun Son, Xiangyu Wu, Neal Livesay, Evelio Mora, '''Kaustubh Shivdikar''', José L. Abellán, Ajay Joshi, David Kaeli, John Kim | ||
+ | |} | ||
+ | |||
+ | ==.== | ||
+ | [[File:network logo.png|alt=GNN Logo|right|frameless|82x82px|GNN Logo]] | ||
− | ======MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training====== | + | ======[https://wiki.kaustubh.us/w/img_auth.php/maxk.pdf MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training]====== |
{{Nutshell|Presented MaxK non-linearity as a universal approximator to speedup GNN training|title=Paper}} | {{Nutshell|Presented MaxK non-linearity as a universal approximator to speedup GNN training|title=Paper}} | ||
− | (ASPLOS 2024) [PDF] [RG] | + | (ASPLOS 2024) [[https://wiki.kaustubh.us/w/img_auth.php/maxk.pdf PDF]] [[https://github.com/harveyp123/MaxK-GNN GitHub]] [RG] |
{| class="wikitable mw-collapsible mw-collapsed" | {| class="wikitable mw-collapsible mw-collapsed" | ||
|+Abstract | |+Abstract | ||
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− | + | ==.== | |
− | + | [[File:AMD MI100 GPU.png|right|frameless|226x226px|AMD MI100 GPU]] | |
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======[https://wiki.kaustubh.us/w/img_auth.php/GME.pdf GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption]====== | ======[https://wiki.kaustubh.us/w/img_auth.php/GME.pdf GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption]====== | ||
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− | + | ==.== | |
− | + | [[File:V100 GPU.png|right|frameless|168x168px]] | |
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======[https://wiki.kaustubh.us/w/img_auth.php/FHE_IEEE_Micro.pdf Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs]====== | ======[https://wiki.kaustubh.us/w/img_auth.php/FHE_IEEE_Micro.pdf Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs]====== | ||
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([https://ieeexplore.ieee.org/document/10068510 IEEE MICRO 2023]) [[https://wiki.kaustubh.us/w/img_auth.php/FHE_IEEE_Micro.pdf PDF]] [[https://www.researchgate.net/publication/369197973_Accelerating_Finite_Field_Arithmetic_for_Homomorphic_Encryption_on_GPUs RG]] | ([https://ieeexplore.ieee.org/document/10068510 IEEE MICRO 2023]) [[https://wiki.kaustubh.us/w/img_auth.php/FHE_IEEE_Micro.pdf PDF]] [[https://www.researchgate.net/publication/369197973_Accelerating_Finite_Field_Arithmetic_for_Homomorphic_Encryption_on_GPUs RG]] | ||
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======'''[https://wiki.kaustubh.us/w/img_auth.php/FHE_SEED_2022.pdf Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/FHE_SEED_2022.pdf Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs]'''====== | ||
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− | + | [[File:Hacker icon.png|right|frameless|90x90px]] | |
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======'''[https://wiki.kaustubh.us/w/img_auth.php/JAXED_Reverse_Engineering_DNN_Architectures_Leveraging_JIT_GEMM_Libraries.pdf JAXED: Reverse Engineering DNN Architectures Leveraging JIT GEMM Libraries]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/JAXED_Reverse_Engineering_DNN_Architectures_Leveraging_JIT_GEMM_Libraries.pdf JAXED: Reverse Engineering DNN Architectures Leveraging JIT GEMM Libraries]'''====== | ||
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− | + | [[File:Mini GNN.png|right|frameless|98x98px]] | |
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======'''[https://wiki.kaustubh.us/w/img_auth.php/GNNMark.pdf GNNMark: A benchmark suite to characterize graph neural network training on GPUs]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/GNNMark.pdf GNNMark: A benchmark suite to characterize graph neural network training on GPUs]'''====== | ||
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− | + | [[File:Core Image SMASH.png|right|frameless|45x45px]] | |
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======'''[https://wiki.kaustubh.us/w/img_auth.php/SMASH_Thesis.pdf SMASH: Sparse Matrix Atomic Scratchpad Hashing]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/SMASH_Thesis.pdf SMASH: Sparse Matrix Atomic Scratchpad Hashing]'''====== | ||
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======'''[https://wiki.kaustubh.us/w/img_auth.php/SC_18_Cluster_Contest_Paper.pdf Student cluster competition 2018, team northeastern university: Reproducing performance of a multi-physics simulations of the Tsunamigenic 2004 Sumatra Megathrust earthquake on the AMD EPYC 7551 architecture]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/SC_18_Cluster_Contest_Paper.pdf Student cluster competition 2018, team northeastern university: Reproducing performance of a multi-physics simulations of the Tsunamigenic 2004 Sumatra Megathrust earthquake on the AMD EPYC 7551 architecture]'''====== | ||
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======'''[https://wiki.kaustubh.us/w/img_auth.php/BARC_speeding.pdf Speeding up DNNs using HPL based Fine-grained Tiling for Distributed Multi-GPU Training]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/BARC_speeding.pdf Speeding up DNNs using HPL based Fine-grained Tiling for Distributed Multi-GPU Training]'''====== | ||
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[[https://www.researchgate.net/publication/357766887_Speeding_up_DNNs_using_HPL_based_Fine-grained_Tiling_for_Distributed_Multi-GPU_Training RG]] | [[https://www.researchgate.net/publication/357766887_Speeding_up_DNNs_using_HPL_based_Fine-grained_Tiling_for_Distributed_Multi-GPU_Training RG]] | ||
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======'''[https://wiki.kaustubh.us/w/img_auth.php/Video_Steganography.pdf Video steganography using encrypted payload for satellite communication]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/Video_Steganography.pdf Video steganography using encrypted payload for satellite communication]'''====== | ||
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[[https://www.researchgate.net/publication/317702110_Video_steganography_using_encrypted_payload_for_satellite_communication RG]] | [[https://www.researchgate.net/publication/317702110_Video_steganography_using_encrypted_payload_for_satellite_communication RG]] | ||
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======'''[https://wiki.kaustubh.us/w/img_auth.php/missing_middle.pdf Missing 'Middle Scenarios' Uncovering Nuanced Conditions in Latin America's Housing Crisis]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/missing_middle.pdf Missing 'Middle Scenarios' Uncovering Nuanced Conditions in Latin America's Housing Crisis]'''====== | ||
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[[https://www.researchgate.net/publication/361864952_Missing_Middle_Scenarios_Uncovering_Nuanced_Conditions_in_Latin_America's_Housing_Crisis RG]] | [[https://www.researchgate.net/publication/361864952_Missing_Middle_Scenarios_Uncovering_Nuanced_Conditions_in_Latin_America's_Housing_Crisis RG]] | ||
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======'''[https://wiki.kaustubh.us/w/img_auth.php/dynamic_power.pdf Dynamic power allocation using Stackelberg game in a wireless sensor network]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/dynamic_power.pdf Dynamic power allocation using Stackelberg game in a wireless sensor network]'''====== | ||
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[[https://www.researchgate.net/publication/294873909_Dynamic_Power_Allocation_using_Stackelberg_Game_in_a_Wireless_Sensor_Network RG]] | [[https://www.researchgate.net/publication/294873909_Dynamic_Power_Allocation_using_Stackelberg_Game_in_a_Wireless_Sensor_Network RG]] | ||
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======'''[https://wiki.kaustubh.us/w/img_auth.php/automatic_image.pdf Automatic image annotation using a hybrid engine]'''====== | ======'''[https://wiki.kaustubh.us/w/img_auth.php/automatic_image.pdf Automatic image annotation using a hybrid engine]'''====== | ||
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*The Prime Hexagon (Best Poster Award) [[https://wiki.kaustubh.us/w/img_auth.php/Prime_Hexagon.pdf PDF]] | *The Prime Hexagon (Best Poster Award) [[https://wiki.kaustubh.us/w/img_auth.php/Prime_Hexagon.pdf PDF]] | ||
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Latest revision as of 08:19, 30 April 2024
Hi, I am Kaustubh, a Ph.D. candidate studying computer engineering in NUCAR lab at Northeastern University with my advisor David Kaeli. My research focuses on designing hardware accelerators for sparse graph workloads.
My expertise lies in:
- Computer Architecture Simulator Design
- Graph Neural Network Accelerators
- Sparse Matrix Accelerators
- Homomorphic Encryption Accelerators
- GPU Kernel Design
Contact:
- shivdikar.k [at] northeastern [dot] edu
- mail [at] kaustubh [dot] us
[Resume]
Education
- PhD - Computer Engineering, Northeastern University [May 2024]
- MS - Electrical and Computer Engineering, Northeastern University [May 2021]
- BS - Electrical Engineering, Veermata Jijabai Technological Institute [May 2016]
Work
- Summer-Fall 2020 Coop: Parallel Computing Lab @ Intel Labs with Fabrizio Petrini.
- Summer-Fall 2019 Coop: Parallel Computing Lab @ Intel Labs with Fabrizio Petrini.
- Summer-Fall 2018 Coop: Mobile Robotics @ Omron Adept with George Paul.
Recent News
- June 2022: Mentored Lina Adkins for the GNN Acceleration project at REU-Pathways program
- May 2022: Served as Submission co-chair for HPCA 2023 conference.
- Jan 2020: Taught the GPU Programming Course at NEU
- April 2019: Graduate Innovator Award at the RISE 2019 Research Expo for our poster Pi-Tiles
- April 2018: Best Poster Award at the RISE 2018 Research Expo for our poster The Prime Hexagon
- Nov 2018: Mentored the NEU team for Student Cluster Contest at Super Computing Conference 2018
- Nov 2017: Joined the NEU Team for Student Cluster Contest at Super Computing Conference 2017
Publications
NeuraChip: Accelerating GNN Computations with a Hash-based Decoupled Spatial Accelerator
NeuraChip in a nutshell: Decoupled multiplication and addition operations to speedup GNNs. |
(ISCA 2024) [PDF] [RG] [Slides] [GitHub] [Website]
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Enabling Accelerators for Graph Computing
Thesis in a nutshell: Software and Hardware enhancements for GNNs |
(Ph.D. Thesis) [PDF]
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Scalability Limitations of Processing-in-Memory using Real System Evaluations
Paper in a nutshell: Suggest interconnects for PIM nodes to enable efficient all-to-all communication. |
(ACM SIGMETRICS 2024) [PDF] [RG]
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MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training
Paper in a nutshell: Presented MaxK non-linearity as a universal approximator to speedup GNN training |
(ASPLOS 2024) [PDF] [GitHub] [RG]
.
GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption
GME in a nutshell: Enhanced the AMD MI-100 GPU on-chip network to accelerate Homomorphic Encryption. |
(IEEE/ACM MICRO 2023) [PDF] [RG] [Slides]
Abstract |
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Fully Homomorphic Encryption (FHE) enables the processing of encrypted data without decrypting it.
FHE has garnered significant attention over the past decade as it supports secure outsourcing of data processing to remote cloud services. Despite its promise of strong data privacy and security guarantees, FHE introduces a slowdown of up to five orders of magnitude as compared to the same computation using plaintext data. This overhead is presently a major barrier to the commercial adoption of FHE. In this work, we leverage GPUs to accelerate FHE, capitalizing on a well-established GPU ecosystem available in the cloud. We propose GME, which combines three key microarchitectural extensions along with a compile-time optimization to the current AMD CDNA GPU architecture. First, GME integrates a lightweight on-chip compute unit (CU)-side hierarchical interconnect to retain ciphertext in cache across FHE kernels, thus eliminating redundant memory transactions. Second, to tackle compute bottlenecks, GME introduces special MOD-units that provide native custom hardware support for modular reduction operations, one of the most commonly executed sets of operations in FHE. Third, by integrating the MOD-unit with our novel pipelined 64-bit integer arithmetic cores (WMAC-units), GME further accelerates FHE workloads by 19%. Finally, we propose a Locality-Aware Block Scheduler (LABS) that exploits the temporal locality available in FHE primitive blocks. Incorporating these microarchitectural features and compiler optimizations, we create a synergistic approach achieving average speedups of 796x, 14.2x, and 2.3x over Intel Xeon CPU, NVIDIA V100 GPU, and Xilinx FPGA implementations, respectively. |
Authors: Kaustubh Shivdikar, Yuhui Bao, Rashmi Agrawal, Michael Shen, Gilbert Jonatan, Evelio Mora, Alexander Ingare, Neal Livesay, José L. Abellán, John Kim, Ajay Joshi, David Kaeli |
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Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs
Paper in a nutshell: Optimized modulo "%" operator on NVIDIA V100 GPU to speedup Homomorphic Encryption. |
(IEEE MICRO 2023) [PDF] [RG]
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Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs
Paper in a nutshell: Incorporated NVIDIA V100's shared memory to accelerate Homomorphic Encryption. |
(SEED 2022) [PDF][Slides] [RG]
Abstract |
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Homomorphic Encryption (HE) enables users to securely outsource both the storage and computation of sensitive data to untrusted servers. Not only does FHE offer an attractive solution for security in cloud systems, but lattice-based FHE systems are also believed to be resistant to attacks by quantum computers. However, current FHE implementations suffer from prohibitively high latency. For lattice-based FHE to become viable for real-world systems, it is necessary for the key bottlenecks---particularly polynomial multiplication---to be highly efficient.
In this paper, we present a characterization of GPU-based implementations of polynomial multiplication. We begin with a survey of modular reduction techniques and analyze several variants of the widely-used Barrett modular reduction algorithm. We then propose a modular reduction variant optimized for 64-bit integer words on the GPU, obtaining a 1.8x speedup over the existing comparable implementations.
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FHE protects against network insecurities in untrusted cloud services, enabling users to securely offload sensitive data |
Authors: Kaustubh Shivdikar, Gilbert Jonatan, Evelio Mora, Neal Livesay, Rashmi Agrawal, Ajay Joshi, José L. Abellán, John Kim, David Kaeli |
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JAXED: Reverse Engineering DNN Architectures Leveraging JIT GEMM Libraries
JAXED in a nutshell: Exposed software cache's vulnerability with a side-channel attack. |
(SEED 2021) [PDF] [Slides] [Poster] [RG]
Abstract |
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General matrix multiplication (GEMM) libraries on x86 architectures have recently adopted Just-in-time (JIT) based optimizations to dramatically reduce the execution time of small and medium-sized matrix multiplication. The exploitation of the latest CPU architectural extensions, such as the AVX2 and AVX-512 extensions, are the target for these optimizations. Although JIT compilers can provide impressive speedups to GEMM libraries, they expose a new attack surface through the built-in JIT code caches. These software-based caches allow an adversary to extract sensitive information through carefully designed timing attacks. The attack surface of such libraries has become more prominent due to their widespread integration into popular Machine Learning (ML) frameworks such as PyTorch and Tensorflow.
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Attack Surface: After the victim’s execution, the victim leaves behind information about its model hyperparameters in the JIT code cache. The attacker probes this JIT code cache through the attacker’s ML model and observes timing information to determine the victim’s model hyperparameters. |
Authors: Malith Jayaweera, Kaustubh Shivdikar, Yanzhi Wang, David Kaeli |
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GNNMark: A benchmark suite to characterize graph neural network training on GPUs
GNNMark in a nutshell: Created a standardized suite of GNN workloads to benchmark GPUs. |
(ISPASS 2021) [PDF] [RG]
Abstract |
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Graph Neural Networks (GNNs) have emerged as a promising class of Machine Learning algorithms to train on non-euclidean data. GNNs are widely used in recommender systems, drug discovery, text understanding, and traffic forecasting. Due to the energy efficiency and high-performance capabilities of GPUs, GPUs are a natural choice for accelerating the training of GNNs. Thus, we want to better understand the architectural and system level implications of training GNNs on GPUs. Presently, there is no benchmark suite available designed to study GNN training workloads.
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Graph Neural Network Analysis |
Authors: Trinayan Baruah, Kaustubh Shivdikar, Shi Dong, Yifan Sun, Saiful A Mojumder, Kihoon Jung, José L. Abellán, Yash Ukidave, Ajay Joshi, John Kim, David Kaeli |
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SMASH: Sparse Matrix Atomic Scratchpad Hashing
SMASH in a nutshell: Optimized SpGEMM for Intel's PIUMA architecture. |
(MS Thesis, 2021) [PDF] [RG]
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Student cluster competition 2018, team northeastern university: Reproducing performance of a multi-physics simulations of the Tsunamigenic 2004 Sumatra Megathrust earthquake on the AMD EPYC 7551 architecture
Paper in a nutshell: Optimizing earthquake simulation workload on AMD CPUs. |
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Speeding up DNNs using HPL based Fine-grained Tiling for Distributed Multi-GPU Training
Paper in a nutshell: Evaluating the cluster equipped with NVIDIA GPUs using the Linpack benchmark. |
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Video steganography using encrypted payload for satellite communication
Paper in a nutshell: Concealing secret messages in videos. |
(Aerospace Conference 2017) [PDF] [RG]
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Missing 'Middle Scenarios' Uncovering Nuanced Conditions in Latin America's Housing Crisis
Paper in a nutshell: Integrating LSTM models with Latin American housing data to devise solutions. |
(Cityscape 2017) [PDF] [RG]
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Dynamic power allocation using Stackelberg game in a wireless sensor network
Paper in a nutshell: Employing game theory for power distribution models. |
(Aerospace Conference 2016) [PDF] [RG]
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Automatic image annotation using a hybrid engine
Paper in a nutshell: A hybrid engine that merges feature extraction with language models. |
(Indicon 2015) [PDF] [RG]
Posters
- FHE [PDF]
- JAXED [PDF]
- Pi-Tiles (Graduate Innovator Award) [PDF]
- The Prime Hexagon (Best Poster Award) [PDF]
What is KTB Wiki?
KTB Wiki, because the best way to store your knowledge is in an indexed SQL database.
This website was built on KTB Wiki. KTB wiki is my side project/attempt to consolidate knowledge gained during my Ph.D. journey. Though many other platforms provide similar service, the process of creating KTB Wiki was a learning experience since it taught me concepts of indexing, load balancing, and in-memory file systems. KTB Wiki was built using MediaWiki and is intended for research purposes only.
Interesting Reads